Calculating a + sign(A) in a single instruction cycle

ABSTRACT

The expression A+sign(A), where A is a signed binary integer represented in 2&#39;s complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing(A+1) when A is less than zero, bit-complementing A when A is equal to zero, bit-complementing(A-1) when A is greater than zero and odd, and bit-complementingall bits except a least significant bit of A when A is greater than zero and even. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to computer arithmetic, and moreparticularly to calculating the expression A+sign(A) for signed binaryintegers.

2. Description of Related Art

The Moving Picture Experts Group (MPEG) standard has emerged as thedominant standard for compressed digital video. The MPEG-1 standardspecifies a compressed video bit-stream rate of approximately 1.5megabits per second, and a compressed stereo audio bit-stream rate ofapproximately 250 kilobits per second. The second standard, MPEG-2, willspecify compression rates for higher-bandwidth distribution media, andis in the process of being formalized. To meet the MPEG standard, videoand audio compression and decompression products must rapidly processthe various algorithms used to implement the MPEG standard.

In MPEG video signal processing, the basic video information processingunit is typically a macro-block, which has a 16×16 pixel matrixcomprising four 8×8 luminance blocks, and two 8×8 chrominance blocks.Each pixel in a luminance block or chrominance block has an outputcorresponding to an unsigned integer number, and each macro-block ispart of a much larger luminance or chrominance frame, as the case maybe.

MPEG video signal processing includes a computation requirement forcalculating sign 3 expressions such as 2A+sign(A) for each pixel in ablock, where A is a signed binary integer, sign (A) is equal to one whenA is greater than zero, sign(A) is equal to zero when A is zero, andsign (A) is equal to negative one when A is less than zero. Forcompleteness, it is useful to be able to calculate other sign 3expressions, such as A+sign(A).

FIG. 1 is a flow chart of algorithm 100, which is known, for calculatingA+sign(A). At step 102, signed binary operand A is obtained. Decisionstep 104 tests whether A is zero. If A is zero, the algorithm branchesto end step 112 since A provides A+sign(A). If A is nonzero, thealgorithm branches to decision step 106 which tests whether A isnegative. If A is negative, at step 108 A is decremented to obtain A-1,and the algorithm terminates at end step 112 since A-1 providesA+sign(A). Returning to decision step 106, if A nonnegative (andtherefore greater than zero since A is nonzero) then at step 110 A isincremented to obtain A+1, and the algorithm terminates at end step 112since A+1 provides A+sign(A). Conventional variations to algorithm 100are apparent. For instance, A can be tested for being negative before Ais tested for being zero. Although algorithm 100 and related variationsare simple to implement, they normally require several instructioncycles.

Moreover, providing zero detect at decision step 104 may require a largeamount of chip area or several instruction cycles using conventionalapproaches. For instance, zero detect of an n-bit operand can beprovided by an n-bit OR gate coupled to an inverter. The OR gate outputsa zero, which the inverter converts to a one, only when the operandconsists of zero's. Drawbacks to this approach include the increasedfan-in of the OR gate, which increases chip area, and the delayassociated with ORing each bit of the operand. Another known techniquefor zero detect of a binary operand includes serially right-shifting theoperand, and inspecting the shifted-out bits one at a time. As soon as ashifted-out bit of one is detected then the operand must be nonzero,whereas if all shifted-out bits are zero's then the operand must bezero. A drawback to this approach is that the right-shifting operationcan be relatively time consuming and particularly difficult to implementin a single instruction cycle.

Accordingly, a need exists for calculating A+sign(A) in a rapid andefficient manner.

SUMMARY OF THE INVENTION

An object of the invention is to provide rapid and efficient calculationof A+sign(A). In accordance with a preferred aspect of the invention,A+sign(A) is calculated by a general purpose computer in a singleinstruction cycle.

The present invention includes a method of operating a circuit tocalculate A+sign(A). One embodiment of the method includesbit-complementingA to obtain A, bit-complementing (A+1) to obtainA+sign(A) when A is less than zero, bit-complementing A to obtain A +sign(A) when A is equal to zero, bit-complementing(A-1) to obtainA+sign(A) when A is greater than zero and A is odd, andbit-complementingall bits except a least significant bit of A to obtainA+sign(A) when A is greater than zero and A is even. Preferably, themethod includes setting a constant C to one and selecting thebit-complement of the least significant bit of (A+1) when A is less thanzero, setting the constant C to zero and selecting the bit-complement ofthe least significant bit of A when A is zero, setting the constant C tonegative one and selecting the bit-complement of the least significantbit of (A-1) when A is greater than zero and A is odd, and setting theconstant C to zero and selecting the least significant bit of A when Ais greater than zero and A is even. Setting the constant C is inresponse to a sign bit of A, indicative of whether A is positive ornegative, and a least significant bit of A, indicative of whether A isodd or even. The selecting is in response to the sign bit of A, theleast significant bit of A, and a zero detect flag, indicative ofwhether A is zero or nonzero.

Furthermore, zero detect of A can be provided by determining whether afirst carry-out bit from (A+0) and a second carry-out bit from (A+1)have different logical values.

The present invention also includes an apparatus for calculatingA+sign(A). In one embodiment, the apparatus includes first and secondinverter circuits, a data selector circuit, an adder circuit, and amultiplexer in combination. The first inverter circuit provides thebit-complement of A to a first operand input of the adder circuit. Thedata selector circuit sets a constant C to one when A is less than zero,to zero when A is zero, to zero when A is greater than zero and even,and to negative one when A is greater than zero and odd. The dataselector circuit provides the constant C to a second operand input ofthe adder circuit. The adder circuit calculates (A+1) at a sum outputwhen A is less than zero, and (A+0) at the sum output when A is equal tozero or when A is greater than zero and even, and (A-1) at the sumoutput when A is greater than zero and odd. The second inverter circuitprovides the bit-complement of the sum output. Finally, the multiplexerselects the least significant bit of the sum output when A is greaterthan zero and even, and otherwise selects the least significant bit ofthe second inverter circuit. Preferably, the adder circuit generates afirst carry-out bit from the sum output and a second carry-out bit froma sum-plus-one output, and a zero detect circuit determines whether A iszero by determining whether the first and second carry-out bits havedifferent logical values.

These and other objects, features and advantages of the invention willbe further described and more readily apparent from a review of thedetailed description of the preferred embodiments which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, in which likereference characters indicate like parts:

FIG. 1 is a flow chart of a known algorithm for calculating A+sign(A).

FIG. 2 is a flow chart of an algorithm for calculating A+sign(A) inaccordance with an embodiment of the present invention;

FIG. 3 is a block diagram of a logic circuit for calculating A+sign(A)in accordance with an embodiment of the present invention;

FIG. 4 is a block diagram of a logic circuit for calculating A+sign(A)in accordance with another embodiment of the present invention;

FIG. 5 is a block diagram of a sum and sum-plus-one adder suitable foruse in the logic circuit of FIG. 4; and

FIG. 6 is a block diagram of a logic circuit for calculating A+sign(A)in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention calculates A+sign(A) in a single instruction cycleby bit-complementing A to obtain A, bit-complementing(A+1) to obtainA+sign(A) when A is less than zero, bit-complementing A to obtainA+sign(A) when A is equal to zero, bit-complementing (A-1) to obtainA+sign(A) when A is greater than zero and A is odd, andbit-complementingall bits except a least significant bit of A to obtainA+sign(A) when A is greater than zero and A is even.

As used herein, A is a signed binary integer represented in 2'scomplement form. As mentioned above, sign(A) is equal to one when A isgreater than zero, sign(A) is equal to zero when A is zero, and sign(A)is equal to negative one when A is less than zero. Determining whether Ais positive (including zero) or negative is accomplished by inspectionof its most significant bit ("MSB"). For a positive A the MSB=0, whereasfor a negative A the MSB=1. Bit-complementing is equivalent to a 1'scomplement operation. For instance, A designates the bit-complement ofA. Finally, incrementing refers to increasing by one.

The present invention is perhaps best understood by considering some ofthe underlying mathematics. In 2's complement representation, thenegative of an integer number is provided by taking the 1's complementof the number and then incrementing, that is,

    -A=A+1                                                     (1)

    A=-A-1                                                     (2)

Consider the following algebraic manipulations for A+sign(A) when A isless than zero:

    A+sign(A)=A+(-1)                                           (3)

    A+sign(A)=A-1                                              (4)

    A+sign(A)=-(-A)-1                                          (5)

    A+sign(A)=-A                                               (6)

    A+sign(A)=(-A-1)+1                                         (7)

    A+sign(A)=A+1                                              (8)

Consider the following algebraic manipulations for A+sign(A) when A isequal to zero:

    A+sign(A)=A+(0)                                            (9)

    A+sign(A)=A                                                (10)

    A+sign(A)=A                                                (11)

Consider the following algebraic manipulations for A+sign(A) when A isgreater than zero:

    A+sign(A)=A+(1)                                            (12)

    A+sign(A)=A+2-1                                            (13)

    A+sign(A)=-(-A-2)-1                                        (14)

    A+sign(A)=-A-2                                             (15)

    A+sign(A)=(-A-1)-1                                         (16)

    A+sign(A)=A-1                                              (17)

Consider the following algebraic manipulations for A+sign(A) when A isgreater than zero:

    A+sign(A)=A+(1)                                            (18)

    A+sign(A)=A+1-1+1                                          (19)

    A+sign(A)=(-(-A-1)-1)+1                                    (20)

    A+sign(A)=-A-1+1                                           (21)

    A+sign(A)=A+1                                              (22)

In accordance with expression (8), when A is less than zero, A+sign(A)is provided by bit-complementing (A+1). In accordance with expression(11), when A is equal to zero, A +sign(A) is provided bybit-complementing A (or A+0). In accordance with expression (17), when Ais greater than zero and A is odd, A+sign(A) is provided bybit-complementing (A-1). In accordance with expression (22), when A isgreater than zero and A is even, A +sign(A) is provided bybit-complementing A and then incrementing the result.

Referring still to expression (22), it is noted that if A is greaterthan zero and even, the least significant bit (LSB) of A must alwaysmust always be a zero, therefore the LSB of A must always be a one, theLSB of A must always be a zero, and the LSB of A+1 must always be a one.Therefore, A+1 can be obtained in several ways, including (1)incrementing A; (2) providing A and setting the LSB to one; (3) settingthe LSB of A to zero and then bit-complementing the intermediate result;and (4) providing A and selecting the LSB of A instead of A. In allcases, A+1 is equivalent to bit-complementingall bits except the LSB ofA.

FIG. 2 is a flow chart of algorithm 200 for calculating A+sign(A) inaccordance with an embodiment of the invention. At step 202, signedbinary operand A is obtained. Decision step 204 tests whether A isnegative. If A is negative, at step 206 A is bit-complemented, at step208 the sum A+1 is calculated, at step 210 the sum A+1 isbit-complemented to provide the result, and the algorithm terminates atend step 226. Returning to decision step 204, if A is nonnegative, atstep 212 A is bit-complemented, and decision step 214 tests whether A isodd. If A is odd (and therefore greater than zero since A is alsononnegative)then at step 216 the difference A-1 is calculated, at step218 the difference A-1 is bit-complemented to provide the result, andthe algorithm terminates at end step 226. Returning to decision step214, if A is not odd then at step 220 A is bit-complemented, anddecision step 222 tests whether A is zero. If A is zero, thebit-complement of A provides the result and the algorithm terminates atend step 226. If A is nonzero (and therefore greater than zero and evensince A is nonnegative and not odd), then at step 224 the bit-complementof A is incremented to provide the result and the algorithm terminatesat end step 226.

Variations to algorithm 200 are apparent. For instance, A can bebit-complemented before the sign bit (or complemented sign bit) of A isinspected. For each value of A, the expressions A+1, A-1 and A+1 can becalculated (concurrently if desired) with the appropriate expressionselected depending on whether A is less than zero, equal to zero,greater than zero and odd, or greater than zero and even, respectively.Likewise, A can be tested for being less than zero, equal to zero,greater than zero and odd, or greater than zero and even before theappropriate expression is calculated.

Zero detect of A can be accomplished by bit-complementing A, andinspecting a carry-out bit from the MSB position generated byincrementing the bit-complement of A. The carry-out bit is a one only ifthe bit-complement of A is a string of one's, otherwise the carry-outbit is a zero. Furthermore, the bit-complement of A is a string of one'sonly if A is a string of zero's. Therefore, the carry-out bit generatedby incrementing the bit-complement of A is a one only if A is zero. In asimilar manner, zero detect of A can be accomplished by decrementing A,and inspecting a carry-out bit generated by incrementing A-1.

Zero detect of A can also be accomplished by generating a firstcarry-out bit from the MSB position of the sum A+0, generating a secondcarry-out bit from the MSB position of the sum A+1, and determiningwhether the first and second carry-out bits have different logicalvalues. When A is zero, the first sum is a string of one's, the secondsum is a string of zero's, and the first and second carry-out bits willhave different logical values. Likewise, when A is nonzero, the firstand second carry-out bits will have identical logical values.Advantageously, the first and second carry-out bits can be generatedconcurrently to provide rapid zero detect. Furthermore, the first andsecond carry-out bits can be generated without (or before) actuallysumming the numbers, for instance by use of PG generator sections andcarry chains.

Thus, if A is an n-bit string of zero's, A+0 is an n-bit string of one'sthat generates a first carry-out bit of zero from the MSB position, andA+1 is an n-bit string of zero's that generates a second carry-out bitof one from the MSB position. Accordingly, the first and secondcarry-out bits have different logical values since A is zero.

The sums A+0 and A+1 can be generated by applying A and a constant C ofzero to a sum and sum-plus-one adder. Remarkably, the sums A+0 and A+1can be used for both calculating A+sign(A) and determining whether A iszero.

Further details regarding zero detect are set forth in U.S. applicationSer. No. 08/658,454, filed Jun. 5, 1996, entitled "Zero Detect ForBinary Sum" by R. Wong, which is incorporated herein by reference.

With regards to overflow, if A is an n-bit number, and A+sign(A) is ann-bit result, then overflow may occur. In particular, if A has themaximum positive or negative integer value, then adding sign(A) willcause overflow. Also, when overflow occurs, the MSB (or sign bit) of Aand the MSB (or sign bit) of the result have different logical values.Therefore, overflow can be detected by EXCLUSIVE-ORing of the MSB of Aand the MSB of the result. Furthermore, when overflow occurs, it may bedesirable to clamp the result to A, which already represents the maximumpositive or negative integer value.

Alternatively, if A is an n-bit number and A+sign(A) is at least an n+1bit result, then overflow does not occur. That is, an n+1 bit resultaccommodates A+sign(A), since A +sign(A) does not exceed 2A.

Various examples of calculating A+sign(A), in accordance with algorithm200, where A is less than zero, with the possibility of overflow, arelisted below in Table 1. Overflow occurs when the sign bit of A has adifferent logical value than the sign bit of the result. Forillustration purposes, A is a 4-bit operand, and A+sign(A) is a 4-bitresult.

                  TABLE 1                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS LESS THAN ZERO                             WITH POSSIBILITY OF OVERFLOW                                                  Operand   A           A + 1   -----.sub.--A + 1                               (decimal)                      A + sign(A)!                                   ______________________________________                                        1000      1000          0111  1000                                            (decimal -8)                                                                            ↓    + 0001  ↓                                                  0111        0 1000  0111                                                                          (overflow)                                      1010      1010          0101  0110                                            (decimal -6)                                                                            ↓    + 0001  ↓                                                  0101        0 0110  1001                                                                          (decimal -7)                                    1101      1101          0010  0011                                            (decimal -3)                                                                            ↓    + 0001  ↓                                                  0010        0 0011  1100                                                                          (decimal -4)                                    1111      1111          0000  0001                                            (decimal -1)                                                                            ↓    + 0001  ↓                                                  0000        0 0001  1110                                                                          (decimal -2)                                    ______________________________________                                    

Various examples of calculating A+sign(A), in accordance with algorithm200, where A is less than zero, without the possibility of overflow, arelisted below in Table 2. For illustration purposes, A is a 4-bitoperand, and A+sign(A) is a 5-bit result.

                  TABLE 2                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS LESS THAN ZERO                             WITHOUT POSSIBILITY OF OVERFLOW                                               Operand   A sign   A         A + 1 -----.sub.--A + 1                          A         extended                                                            (decimal)                           A + sign(A)!                              ______________________________________                                        1000      11000    11000       00111                                                                             01000                                      (decimal -8)       ↓  + 00001                                                                             ↓                                                      00111     0 01000                                                                             10111                                                                         (decimal -9)                               1010      11010    11010       00101                                                                             00110                                      (decimal -6)       ↓  + 00001                                                                             ↓                                                      00101     0 00110                                                                             11001                                                                         (decimal -7)                               1101      11101    11101       00010                                                                             00011                                      (decimal -3)       ↓  + 00001                                                                             ↓                                                      00010     0 00011                                                                             11100                                                                         (decimal -4)                               1111      11111    11111       00000                                                                             00001                                      (decimal -1)       ↓  + 00001                                                                             ↓                                                      00000     0 00001                                                                             11110                                                                         (decimal -2)                               ______________________________________                                    

A single example of calculating A+sign(A), in accordance with algorithm200, where A is equal to zero, is listed below in Table 3. Forillustration purposes, A is a 4-bit operand, and A+sign(A) is a 4-bitresult.

                  TABLE 3                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS EQUAL TO ZERO                              Operand        A      .sub.-- .sub.--A                                        (decimal               A + sign(A)!                                           ______________________________________                                        0000           0000   1111                                                    (decimal 0)    ↓                                                                             ↓                                                               1111   0000                                                                          (decimal 0)                                             ______________________________________                                    

Various examples of calculating A+sign(A), in accordance with algorithm200, where A is greater than zero and A is even, without the possibilityof overflow, are listed below in Table 4. Overflow does not occur sinceA can not assume the maximum positive integer value (which is odd). Forillustration purposes, A is a 4-bit operand, and A+sign(A) is a 4-bitresult.

                  TABLE 4                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS GREATER THAN ZERO                          AND EVEN WITHOUT POSSIBILITY OF OVERFLOW                                      Operand    A          .sub.-- .sub.--A                                                                     .sub.-- .sub.--A + 1                             (decimal)                     A + sign(A)!                                    ______________________________________                                        0110       0110       1001     0110                                           (decimal 6)                                                                              ↓   ↓                                                                             + 0001                                                      1001       0110   0 0111                                                                        (decimal 7)                                      0100       0100       1011     0100                                           (decimal 4)                                                                              ↓   ↓                                                                             + 0001                                                      1011       0100   0 0101                                                                        (decimal 5)                                      0010       0010       1101     0010                                           (decimal 2)                                                                              ↓   ↓                                                                             + 0001                                                      1101       0010   0 0011                                                                        (decimal 3)                                      ______________________________________                                    

Various examples of calculating A+sign(A), in accordance with algorithm200, where A is greater than zero and A is odd, with the possibility ofoverflow, are listed below in Table 5. Overflow occurs when the sign bitof A has a different logical value than the sign bit of the result. Forillustration purposes, A is a 4-bit operand, and A+sign(A) is a 4-bitresult.

                  TABLE 5                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS GREATER THAN ZERO                          AND ODD WITH POSSIBILITY OF OVERFLOW                                          Operand   A          A - 1    -----.sub.--A - 1                               A                    (A - (-1))                                               (decimal)                      A + sign(A)!                                   ______________________________________                                        0111      0111         1000   0111                                            (decimal 7)                                                                             ↓   + 1111   ↓                                                  1000       1 0111   1000                                                                          (overflow)                                      0101      0101         1010   1001                                            (decimal 5)                                                                             ↓   + 1111   ↓                                                  1010       1 1001   0110                                                                          (decimal 6)                                     0011      0011         1100   1011                                            (decimal 3)                                                                             ↓   + 1111   ↓                                                  1100       1 1011   0100                                                                          (decimal 4)                                     0001      0001         1110   1101                                            (decimal 1)                                                                             ↓   + 1111   ↓                                                  1110       1 1101   0010                                                                          (decimal 2)                                     ______________________________________                                    

Various examples of calculating A+sign(A), in accordance with algorithm200, where A is greater than zero and A is even, without the possibilityof overflow, are listed below in Table 6. For illustration purposes, Ais a 4-bit operand, and A+sign(A) is a 5-bit result.

                  TABLE 6                                                         ______________________________________                                        CALCULATING A + SIGN(A) WHERE A IS GREATER THAN ZERO                          AND ODD WITHOUT POSSIBILITY OF OVERFLOW                                       Operand  A sign   A         A - 1  -----.sub.--A - 1                          A        extended           (A + (-1))                                        (decimal)                           A + sign(A)!                              ______________________________________                                        0111     00111    00111       11000                                                                              10111                                      (decimal 7)       ↓  + 11111                                                                              ↓                                                     11000     1 10111                                                                              01000                                                                         (decimal 8)                                0101     00101    00101       11010                                                                              11001                                      (decimal 5)       ↓  + 11111                                                                              ↓                                                     11010     1 11001                                                                              00110                                                                         (decimal 6)                                0011     00011    00011       11100                                                                              11011                                      (decimal 3)       ↓  + 11111                                                                              ↓                                                     11100     1 11011                                                                              00100                                                                         (decimal 4)                                0001     00001    00001       11110                                                                              11101                                      (decimal 1)       ↓  + 11111                                                                              ↓                                                     11110     1 11101                                                                              00010                                                                         (decimal 2)                                ______________________________________                                    

FIG. 3 is a block diagram of a logic circuit 300 for calculatingA+sign(A) in accordance with an embodiment of the present invention.Inverter circuit 302 includes an operand input coupled to A andgenerates A at an output. Data selector circuit 304 includes an inputcoupled to the sign bit and least significant bit of A, and generates aconstant C at its output set to one when A is less than zero, set tozero when A is zero, set to zero when A is greater than zero and even,and set to negative one when A is greater than zero and odd. Addercircuit 306 includes a first operand input for receiving A and a secondoperand input for receiving the constant C. Adder circuit 306 generatesA+C at a sum output. Thus, adder circuit 306 generates A+1 when A isless than zero, and A+0 when A is zero, A+0 when A is greater than zeroand even, and A-1 when A is positive and odd. Inverter circuit 308includes an operand input coupled to the sum output and generates thebit-complement of the sum output, or A+C. Multiplexer unit 310 receivesA+C, and outputs either A+C or A+C+1 in response to a control input. Ineffect, multiplexer unit 310 automatically outputs all bits except theLSB of A+C, and selects between the LSB of A+C and the LSB of A+C toprovide the LSB of the output. Zero detect circuit 312 determineswhether A is zero or nonzero, and control circuit 314 controlsmultiplexer unit 310 in response to zero detect circuit 312, the signbit of A and the LSB of A. Control circuit 314 causes multiplexer unit310 to output A+C when A is negative, A is zero, or A is greater thanzero and odd, and otherwise causes multiplexer unit 310 to output A+C+1when A is greater than zero and even. In this manner, multiplexer unit310 outputs A+1 when A is less than zero, A when A is equal to zero, A-1when A is greater than zero and odd, and A+1 when A is greater than zeroand even.

Alternatively, if desired, zero detect circuit 312 can be modified toinspect carry-out bits from MSB positions of sum and sum-plus-oneoutputs of adder circuit 306, instead of inspecting A directly. Also,numerous techniques can be used to set the LSB of the result to one(thereby bit-complementing all bits except the LSB of A) when A isgreater than zero and even.

FIG. 4 is a block diagram of a logic circuit 400 for calculatingA+sign(A) in accordance with another embodiment of the invention. Logiccircuit 400 receives a four-bit operand A, consisting of bits A₃, A₂, A₁and A₀, and calculates a four-bit result, consisting of bits R₃, R₂, R₁and R₀. Bits A₃ and R₃ are the MSBs. Logic circuit 400 also generatesoverflow signal OV. Bit A₃ is applied to inverter 402, bit A₂ is appliedto inverter 404, bit A₁ is applied to inverter 406, and bit A₀ isapplied to inverter 408. Inverters 402,404, 406 and 408 generate bits A₃, A₂ , A₁ and A₀ , respectively. Bit A₃ is applied to a first operandinput of half adder 410, bit A₂ is applied to a first operand input ofhalf adder 412, bit A₁ is applied to a first operand input of half adder414, and bit A₀ is applied to a first operand input of half adder 416.

Furthermore, bits A₃ and A₀ are applied to OR gate 418, bits A₃ and A₀are applied to NOR gate 420, the output of NOR gate 420 is applied tosecond operand inputs of half adders 410, 412 and 414, and the output ofOR gate 418 is applied to the second operand input of half adder 416. Inthis fashion, the outputs of NOR gate 420 and OR gate 418 provide aconstant C that is applied to the second operand inputs of half adders410, 412, 414 and 416. When bit A₃ is a one (and thus A is less thanzero), OR gate 418 generates a one, NOR gate 420 generates a zero, andthe constant C is one. When bit A₃ is a zero and bit A₀ is a zero (andthus A is zero, or A is greater than zero and even), OR gate 418generates a zero, NOR gate 420 generates a zero, and the constant C iszero. Finally, when bit A₃ is a zero and bit A₀ is a one, OR gate 418generates a one, NOR gate 420 generates a one, and the constant C isnegative one.

The outputs of half adders 410, 412, 414 and 416 are applied to operandinputs of sum and sum-plus-one adder 422. In particular, sum bit S_(A)of half adder 410 and carry-out bit C_(B) of half adder 412 are appliedto stage 3 of adder 422, sum bit S_(B) of half adder 412 and carry-outbit C_(C) of half adder 414 are applied to stage 2 of adder 422, sum bitS_(C) of half adder 414 and carry-out bit C_(D) of half adder 416 areapplied to stage 1 of adder 422, and sum bit S_(D) of half adder 416 anda zero are applied to stage 0 of adder 422. Accordingly, adder 422generates a sum output, consisting of bits S₃, S₂, S₁ and S₀, and asum-plus-one output, consisting of bits S+1₃, S+1₂, S+1₁ and S+1₀. Adder422 also generates first carry-out bit C_(OUT1) from stage 3 of the sumoutput, and second carry-out bit C_(OUT2) from stage 3 of thesum-plus-one output. In fact, the sum-plus-one output need not begenerated as long as second carry-out bit C_(OUT2) is generated.

Bit S₃ is applied to inverter 424, bit S₂ is applied to inverter 426,bit S₁ is applied to inverter 428, and bit S₀ is applied to inverter430. Inverters 424, 426, 428 and 430 generate bits S₃ , S₂ , S₁ and S₀ ,respectively. Bits S₃ , S₂ and S₁ provide bits R₃, R₂ and R₁,respectively. Furthermore, bits S₀ and S₀ are applied to first andsecond operand inputs of 2:1 multiplexer 432, and select signal SEL isapplied to a control input of multiplexer 432. Multiplexer 432 selectsthe first input thereof and outputs bit S_(O) to provide bit R₀ whensignal SEL is a zero, and multiplexer 432 selects the second inputthereof and outputs bit S₀ to provide bit R₀ when signal SEL is a one.AND gate 434 generates signal SEL as a one when (i) bit A₃ is a one,indicating A is positive, (ii) EXCLUSIVE-OR gate 436 generates a zeroand inverter 438 generates a one, due to first carry-out bit C_(OUT1)from A+0 and second carry-out bit C_(OUT2) from A+1 having identicallogical values, indicating A is nonzero, and (iii) bit A₀ is one,indicating A is even. Thus, AND gate 434 also generates signal SEL as aone only when A is greater than zero and even, and AND gate 434generates signal SEL as a zero when A is less than zero, A is equal tozero, or A is greater than zero and odd.

Overflow detection is provided by EXCLUSIVE-OR gate 440, which indicateswhen bits A₃ and R₃ have different logical values. Accordingly,EXCLUSIVE-OR gate 440 generates overflow signal OV at its output.

Thus, when A is less than zero, bit A₃ is a one, adder 422 generates A+1at the sum output, inverters 424 to 430 generate A+1, signal SEL is azero, multiplexer 432 selects bit S₀ , and the result is A+1. When A isequal to zero, bits A₃ and A₀ are zero's, adder 422 generates A+0 at thesum output, inverters 424 to 430 generate A, signal SEL is a zero,multiplexer 432 selects bit S₀ , and the result is A. When A is greaterthan zero and odd, bit A₃ is a zero and bit A₀ is a one, adder 422generates A-1 at the sum output, inverters 424 to 430 generate A-1,signal SEL is a zero, multiplexer 432 selects bit S₀ , and the result isA-1. Finally, when A is greater than zero and even, bits A₃ and A₀ arezero's, adder 422 generates A+0 at the sum output, inverters 424 to 430generate A, signal SEL is a one, multiplexer 432 selects bit S₀, and theresult is A+1.

FIG. 5 shows an implementation for adder 422. In this implementation,the sum output is provided by a carry look ahead adder that performsfast addition within the basic step time of an instruction cycle.Propagate-generate(PG) sections 502, 504, 506 and 508 receive bits S_(A)and C_(B), S_(B) and C_(C), S_(C) and C_(D), and S_(D) and a zero,respectively, and provide propagate and generate signals P₃ and G₃, P₂and G₂, P₁ and G₁, and P₀ and G₀, respectively. The propagate andgenerate signals are furnished to respective stages of first carry chain510 and second carry chain 512. First carry chain 510 receives a zero asits least significant carry-in bit C_(IN1), and generates carry-out bitsC₃, C₂, C₁ and C₀. Second carry chain 512 receives a one as its leastsignificant carry-inbit C_(IN2), and generates carry-outbits C+1₃, C+1₂,C+1₁ and C+1₀. Carry-out bit C₃ provides first carry-out bit C_(OUT1),and carry-out bit C+1₃ provides second carry-out bit C_(OUT2).Advantageously, first and second carry-out bits C_(OUT1) and C_(OUT2)are generated concurrently. Furthermore, sum generator 514 receives bitsS_(A), C_(B) and C₂ at stage 3, bits S_(B), C_(C), and C₁ at stage 2,bits S_(C), C_(D) and C₀ at stage 1, and bit S_(D) and a pair of zero'sat stage 0. As a result, sum generator 514 generates sum bits S₃, S₂, S₁and S₀. Each stage of sum generator 514 may include, for instance, firstand second two-input EXCLUSIVE-OR gates (not shown), with the inputs ofthe first EXCLUSIVE-OR gate and the second input of the secondEXCLUSIVE-OR gate receiving the bits to be summed, the output of thefirst EXCLUSIVE-OR gate coupled to the first input of the secondEXCLUSIVE-OR gate, and the output of the second EXCLUSIVE-OR gateproviding the sum bit. Also, if the sum-plus-one-output is desired,another sum generator can be utilized in a similar manner. Suitable PGsections, carry chains and sum generators are well-known in the art.

FIG. 6 is a block diagram of a logic circuit 600 for calculatingA+sign(A) in accordance with another embodiment of the invention. Logiccircuit 600 is a simplified version of logic circuit 400. The circuitelements in logic circuit 600 (inverter 602, adder 622, OR gate 634,etc.) correspond to the circuit elements in logic circuit 400 (inverter402, adder 422, OR gate 434, etc.), and the related discussion need notbe repeated. However, logic circuit 600 has no circuit elementscorresponding to half adders 410 to 416 and EXCLUSIVE-OR gate 436.Instead, bit A₃ and the output of NOR gate 620 are applied to stage 3 ofadder 622, bit A₂ and the output of NOR gate 620 are applied to stage 2of adder 622, bit A₁ and the output of NOR gate 620 are applied to stage1 of adder 622, and bit A₀ and the output of OR gate 618 are applied tostage 0 of adder 622. Thus, A is applied to a first operand input ofadder 622, and the constant C is applied to the second operand input ofadder 622. As a result, adder 622 (like adder 422) generates A+1 at thesum output when A is less than zero, A+0 at the sum output when A iszero, A+0 at the sum output when A is greater than zero and even, andA-1 at the sum output when A is greater than zero and odd. Furthermore,since first carry-out bit C_(OUT1) is always a zero when A is zero,second carry-out bit C_(OUT2) is coupled directly to AND gate 634.

Although logic circuit 400 has more circuit elements than logic circuit600, logic circuit 400 can be more easily adapted to accommodate othersign 3 operations.

The description of the invention set forth herein is illustrative, andis not intended to limit the scope of the invention as set forth in thefollowing claims. A general purpose computer or processor can executethe invention in a single instruction cycle (as is preferred) ormultiple instruction cycles. The invention is well-suited for many dataprocessing applications. Variations and modifications of the embodimentsdisclosed herein may be made based on the description set forth herein,without departing from the scope and spirit of the invention as setforth in the following claims.

What is claimed is:
 1. An apparatus for calculating A+sign(A), where Ais a signed binary integer represented in 2's complement form, sign(A)is equal to one when A is greater than zero, sign(A) is equal to zerowhen A is zero, and sign(A) is equal to negative one when A is less thanzero, comprising:a first inverter circuit for bit-complementing A toobtain A; a data selector circuit for setting a constant C to one when Ais less than zero, setting the constant C to zero when A is zero,setting the constant C to zero when A is greater than zero and A iseven, and setting the constant C to negative one when A is greater thanzero and A is odd; an adder circuit for calculating (A+1) at a sumoutput when A is less than zero, for calculating (A+0) at the sum outputwhen A is equal to zero, for calculating (A+0) at the sum output when Ais greater than zero and A is even, and for calculating (A-1) at the sumoutput when A is greater than zero and A is odd; a second invertercircuit for bit-complementing the sum output; and a multiplexer forselecting between a least significant bit of an output of the secondinverter circuit and a least significant bit of the sum output, whereinan output of the second inverter circuit with the least significant bitthereof replaced by an output of the multiplexer provides A+sign(A). 2.The apparatus of claim 1, wherein the adder circuit includes a firstoperand input coupled to A, and a second operand input coupled to theconstant C.
 3. The apparatus of claim 1, including:a zero detect circuitfor determining whether A is zero or nonzero; and a control circuit forcontrolling the multiplexer in response to a sign bit of A, a leastsignificant bit of A, and the zero detect circuit.
 4. The apparatus ofclaim 1, including an overflow detection circuit for indicating overflowwhen a sign bit of A and a sign bit of the output of the second invertercircuit have different logical values.
 5. An apparatus for calculatingA+sign(A), where A is a signed binary integer represented in 2'scomplement form, sign(A) is equal to one when A is greater than zero,sign(A) is equal to zero when A is zero, and sign(A) is equal tonegative one when A is less than zero, comprising:a first invertercircuit having an operand input coupled to A and having an output forproviding a bit-complement of A; a data selector circuit coupled to asign bit of A and a least significant bit of A, and having an output forsetting a constant C to one when A is less than zero, setting theconstant C to zero when A is zero, setting the constant C to zero when Ais greater than zero and A is even, and setting the constant C tonegative one when A is greater than zero and A is odd; an adder circuithaving a first operand input coupled to the output of the first invertercircuit, having a second operand input coupled to the output of the dataselector circuit, and having a sum output representing a sum of thefirst and second operands; a second inverter circuit having an operandinput coupled to the sum output and having an output for providing abit-complement of the sum output; a zero detect circuit for determiningwhether A is zero or nonzero; a multiplexer having a first input coupledto a least significant bit of the output of the second inverter circuit,having a second input coupled to a least significant bit of the sumoutput, and having a select input; and a control circuit, responsive tothe sign bit of A and a least significant bit of A and the zero detectcircuit, having a control output coupled to the select input of themultiplexer, which causes the multiplexer to select the first inputthereof when A is less than zero, equal to zero, or greater than zeroand odd, and causes the multiplexer to select the second input thereofwhen A is greater than zero and even; wherein the output of the secondinverter circuit with the least significant bit thereof replaced by anoutput of the multiplexer provides A+sign(A).
 6. The apparatus of claim5, wherein:the control circuit causes the multiplexer to select thefirst input thereof when the sign bit of A is a one; the control circuitcauses the multiplexer to select the first input thereof when the zerodetect circuit indicates A is zero; the control circuit causes themultiplexer to select the first input thereof when the sign bit of A isa zero and the least significant bit of A is a one; and the controlcircuit causes the multiplexer to select the second input thereof whenthe sign bit of A is a zero and the zero detect circuit indicates A isnonzero and the least significant bit of A is a zero.
 7. The apparatusof claim 5, wherein the data selector circuit includes:an OR gate havinginputs coupled to the sign bit of A and the least significant bit of A,and having an output coupled to a least significant stage of the addercircuit; and a NOR gate having inputs coupled to the sign bit of A and abit-complement of the least significant bit of A, and having an outputcoupled to all stages except the least significant stage of the addercircuit.
 8. The apparatus of claim 5, wherein the adder circuit includesa sum-plus-one output, representing a sum of the first and secondoperands plus one, and the zero detect circuit determines whether afirst carry-out bit from the sum output and a second carry-out bit fromthe sum-plus-one output have different logical values.
 9. The apparatusof claim 8, wherein the first and second carry-out bits are generatedconcurrently.
 10. The apparatus of claim 5, wherein the adder circuitincludes a row of carry save adders that provide the first and secondoperand inputs, a sum adder coupled to the carry save adders forproviding the sum output, and a sum-plus-one adder coupled to the carrysave adders for providing a sum-plus-one output.
 11. The apparatus ofclaim 10, wherein:the sum adder includes propagate-generate sectionscoupled to a first carry chain coupled to a first sum generator thatprovides the sum output, with the first carry chain having a carry-inbit set to zero; and the sum-plus-one adder includes thepropagate-generate sections coupled to a second carry chain coupled to asecond sum generator that provides the sum-plus-one output, with thesecond carry chain having a carry-in bit set to one.